As anyone knows who has recently purchased a computer, computer manufacturers are starting to phase out ISA bus board slots on computers. The newer technology is PCI bus slots. For the past few years, computers contained a few of each type of slot. Now, however, it is much more common to find computers with only PCI bus slots. Since all of the data acquisition boards for CORTEX required the use of an ISA bus slot, it became apparent that a new PCI-based board was needed.

The PCI-DAS1602/12 board was chosen for support in CORTEX, since it is the one that is most similar to the CIO-DAS16 series ISA board. However, there are some very important differences between these two boards. Before buying this new board, please read the details below to make sure that the board will support your data acquisition needs.

Technical details:

Fewer digital channels

It is necessary to first give some background about the CIO-DAS16 series boards. There are two parts to the CIO-DAS16 board. One part contains the functionality of a "DAS16" card, including the analog data lines, and 8 digital lines (4 input/4 output). The second part contains the functionality of a "PIO24" card, including 24 digital lines to be used for digital input and output. The 8 digital lines on the "DAS16" portion of the card are used by Cortex as follows:

Digital In #0 - spike 1
Digital In #1 - spike 2
Digital In #2 - bar up/down
Digital In #3 - bar right/left


Digital Out #0 - reset latches
Digital Out #1 - reward
Digital Out #2 - free
Digital Out #3 - free


The PCI-DAS1602 card also contains a "DAS16" part and a "PIO24"part. However, unlike the CIO-DAS16 series, the "DAS16" portion of the PCI-DAS1602/12 card does not contain the extra 4 digital input and 4 digital outputs. Since the PCI-DAS1602 does not contain these extra lines, it was necessary to use the PIO24 portion of the card for these digital lines. Port C was chosen for this purpose, since it can be split as 4 bits input and 4 bits output. It is configured as follows:
Input:
Port C, bit 0 (pin #67) - spike 1
Port C, bit 1 (pin #68) - spike 2
Port C, bit 2 (pin #69) - bar up/down
Port C, bit 3 (pin #70) - bar right/left

Output:
Port C, bit 4 (pin #71) - reset latches
Port C, bit 5 (pin #72) - reward
Port C, bit 6 (pin #73) - free
Port C, bit 7 (pin #74) - free


As with the CIO-DAS16 and the PIO24 boards, Port A is configured as an input port and Port B is configured as an output port.

In this release, the NO_INIT feature on the DEVICE line of Cortex.cfg will not be supported for the PCI-DAS1602 card. This is because Port C MUST be initialized as outlined above. If Cortex does not initialize Port C before the start of the timing file, there will be problems with the operation of Cortex. In future releases, this restriction may be lifted.


Base address differences

For the CIO-DAS16 boards, there is a single base address that is configurable by the user via jumper settings on the board. Once these jumpers are set, this base address value for the board can not be changed without changing the jumpers. Therefore, the user can confidently supply this value in the DEVICE line of the Cortex.cfg file.

The PCI-DAS1602, on the other hand, is a plug-and-play device, which does not have any onboard jumpers to configure the base addresses. Every time the computer boots up, the BIOS assigns base addresses to the board which will not conflict with the other devices in the computer. It is possible that each time that the computer boots up, the board will have different addresses! Also, instead of having just one base address, the PCI-DAS1602 has five base addresses. Because of this complicated situation, Cortex will just query the BIOS and board internally, to figure out these five addresses. The base address that is supplied on the DEVICE PCIDAS1602 line will be ignored, even though it is a required parameter.


Analog data collection differences For the CIO-DAS16, the analog data is held in two 8-bit registers. The Base+0 register holds the 4 least significant bits, plus the channel number. The Base+1 register holds the 8 most significant bits. For the PCI-DAS1602, however, the analog data register is a 16-bit register, which does not contain the channel number. Instead, the code is written to rely on the "fact" (according to ComputerBoards, Inc) that every time a write is issued to the "channel MUX control register", the board will start collecting with the lowest channel number. Therefore, at the beginning of each trial, a write is issued to the MUX channel register. Internal software counters are then implemented, so that the current channel being read can be determined.

Another analog data collection difference is that the PCI-DAS1602 board does not contain a latched bit for the EOC (end-of-conversion) flag. That is, before analog data is read, the EOC bit should be checked to make sure that the analog-to-digital converter is not busy. Since this EOC bit is not latched, it is virtually impossible to check the bit without putting a waiting loop into the code. A waiting loop could easily destroy the timing of spike data collection. According to the technical support representative at Computerboards, Inc., by structuring the code so that the analog data conversion is triggered, followed by the reading of the digital (spike) lines, before reading the analog data, the timing should be allow for accurate data collection.

These differences in the analog data collection should be transparent to the user. They are mentioned here, since the code was written based on word-of-mouth information from the ComputerBoards, Inc. technical support representatives. The official documentation of the board contains minimal information, and does not specify how to overcome these differences.

Cortex.cfg details:

In order to tell Cortex that you are going to be using the PCI-DAS1602/12 card, you must specify the following lines in your Cortex.cfg file:

DEVICE PCIDAS1602 0x300

As mentioned in the "Fewer Digital Channels" section above, an address must be supplied, but it will be ignored by Cortex. Also, as mentioned above, the INIT and NO_INIT parameter will be ignored. The board will always be initialized automatically. (Note: You can not "split out" the PIO24 portion and DASH16 portion of this card and address them separately like can be done with the CIO-DAS16 card.)

THREAD PCIDAS1602 defaults 1

A2D_GAIN 1 (Will give values between -5 and +5 volts.)

MULTI_SPIKE PCIDAS1602 0x00 2 1 // 2 spikes from Port A, encoded as 1 and 2 MULTI_SPIKE PCIDAS1602 0x02 2 102 // 2 spikes from Port C, encoded as 102 and 103 etc.

Hardware details:

Hardware requirements

The following data acquisition hardware is available from ComputerBoards, Inc. (http://www.computerboards.com):

PCI-DAS1602/12 data acquisition board C100FF cable CIO-TERM100 screw terminal board

Note 1: The connector for this board requires 100 pins. Therefore, the cabling and interface boxes that you have from the CIO-DAS16 boards will not work, since they are 37-pin connectors.

Note 2: The spike channels must still be latched. Therefore, you must either alter the CIO-TERM100 screw terminal board to contain the latches, or have another device that performs the latching. For testing, I use a device built at NIH (RSB #8668) which can latch up to 8 spike channels. The circuit diagram for this device can be found at 74hcLED.GIF

Using DEVinp() and DEVoutp():

The DEVinp() and DEVoutp() functions can be used in a timing file to read and write a byte of data to a specified port number. In the PCI-DAS1602/12 manual, Port A occupies register BADR3+4, PortB occupies BADR3+5, and Port C occupies BADR3+6. Since this is pretty confusing to remember, these port numbers are remapped internally in Cortex, so the more intuitive port numbers can be used:

  PortA = 0   PortB = 1   PortC = 2

For example, assuming that the only device in use is the PCI-DAS1602 board, the code in the timing file could be as follows:

// read a byte from Port A
  val = DEVinp(0, 0x0);

// manually write a byte containing all 1's to Port B
  DEVoutp(0, 0x1, 0xff);

Testing:

Testing has been carried out on the Cortex code using a function generator, and real data from an eye coil. However, it is strongly recommended that you further test the analog and digital data collection in your own setup. Please report any problems to me (tnorden@helix.nih.gov) immediately.